The present invention relates to integrated circuits and to methods for manufacturing them.
VLSI non-volatile memories and other high-voltage integrated circuits usually use two layers of polysilicon, with an appropriate dielectric film in between the two poly layers, to sustain high electric fields with requirements of very low leakage currents. Conventionally, polysilicon films are deposited by LPCVD at about 620.degree. C. The dielectric film can be a thermally grown oxide on the poly 1 layer, or it could be a composite film of oxide/nitride/oxide.
In many kinds of integrated circuit structures, and particularly in non-volatile memories such as EPROMs and EEPROMs, the smoothness of the polysilicon to dielectric interface of poly-to-poly capacitors is critical. That is, normally when an oxide is grown on polysilicon, the polysilicon to dielectric interface will be found to have significant asperities. As is well known, these asperities lead to electric field enhancements, and therefore, to prevent breakdown, the dielectric thickness must be made much larger than would be necessary if the interface were perfectly smooth and flat. Prior art studies have attempted to find answers to the problem of providing a smooth polysilicon to dielectric interface, but without noticeable success. Published literature on research activities relating to this area of art includes the following, articles of which are hereby incorporated by reference
Harbeke et al., LPCVD Polycrystalline Silicon: Growth and Physical Properties of In-Situ Phosphorus Doped and Undoped Films, 44 RCA REVIEW 287 (June 1983). PA0 Chiao et al., Developments in Thin Polyoxides for Non-Volatile Memories, SEMICONDUCTOR INTERNATIONAL, April 1985, Pages 156-159. PA0 Faraone et al., Characterization of Thermally Oxidized n+ Polycrystalline Silicon, 32 IEEE Transactions on Electron Devices--(March 1985). PA0 More reproducible manufacturing process PA0 Reduced leakage current through inter-level capacitors PA0 Higher breakdown voltage in inter-level capacitors PA0 Inter-level capacitors with a given breakdown voltage can be given a higher specific capacitance PA0 Floating gate memory transistors of a given density can be fabricated to program faster.
The Faraone et al paper in the March 1985 IEEE Transactions on Electron Devices suggests depositing the lower polysilicon layer as an amorphous layer rather than as a polycrystalline layer as a means of improving the interface smoothness with an insulating layer of silicon oxide subsequently provided on the polysilicon layer by thermal oxidation. In the latter respect lowering the temperature at which polysilicon is deposited from (e.g.) 620 degrees .degree.C. down to (e.g.) 560 degrees .degree.C., will cause the as-deposited polysilicon film to be amorphous, rather than polycrystalline. This amorphous film will initially have a significantly flatter surface than a polycrystalline film, simply because the grain boundaries and orientation differences of the grains in a polycrystalline film tend to produce some initial surface roughness.
However, a crucial teaching of the present invention, is that, after an amorphous first silicon layer has been deposited, it should be oxidized, but instead a deposited dielectric should be used. The reason for this is that the oxidation process degrades the surface topography for reasons which are not merely thermal. The oxidation process appears to include enhanced diffusion of oxygen along the grain boundaries, and this grain-boundary diffusion itself produces roughness. Thus, chemical vapor deposition of good quality dielectrics will typically proceed at temperatures only slightly lower than those which would be used in a fairly low temperature oxidation step, but the resulting interface smoothness is very much improved, since the effects of oxygen transport along grain boundaries are substantially avoided. Thus, the present invention provides a very much smoother interface than was possible in any prior art method.
Moreover, it should be noted that the discussions of smoother interface in the prior art do not provide a fully manufacturable process, as does the present invention. That is, the prior art processes appear to require very delicate control over the temperatures used in low-temperature oxidation steps, and this tight control degrades manufacturability. Thus, another advantage of the present invention is improved manufacturability.
Moreover, a further teaching of the present invention is that the silicon layer should not be diffusion doped (e.g. using POCl.sub.3), but should be doped by implantation. The implantation process further amorphizes the deposited silicon layer, and thus further contributes to maintaining a small grain size in this layer after the relatively high temperature dielectric deposition step.
It should be noted that, either using the oxidation processes of the prior art or the deposited dielectric processes of the present invention, some grain growth will occur during the high-temperature step. One surprising result of the present invention is that the deposited dielectric maintains an extremely smooth interface, even while this grain growth is occurring, to convert the amorphous as-deposited layer to a polycrystalline layer.
In one class of embodiments of the present invention, the deposited dielectric is configured as an oxide/nitride layered dielectric which is further thermally oxidized to form an oxide/nitride/oxide layered structure; this dielectric is particularly useful in holding the poly-1 interface in place during the thermal cycles.
It is also noted that the only known discussion of the relevance of ion implantation as opposed to diffusion doping occurs in the Faraone communication which is cited as reference 21 in the Faraone article.
This results in a capacitor (where the lower plate is polycrystalline and predominantly silicon) where the breakdown voltage for a given thickness of dielectric is improved, and therefore (to use a commonly accepted figure of merit) the charge stored per unit area on this capacitor can significantly be increased.
In particular, the present invention is especially advantageous in the context of EPROM cells. The coupling between the floating gate and control gate is always desired to be as close as possible, but the dielectric from polysilicon to polysilicon must not break down under the voltages used, and moreover this dielectric must have extremely low leakage currents, to maintain a good storage lifetime. The present invention, by reducing asperities at the polysilicon to dielectric interface, advantageously improves not only breakdown voltage, but also leakage currents at voltages less than breakdown.
Thus, an EPROM or EEPROM cell constructed according to the present invention has major advantages, and substantially improves over any available prior art structure in the respects of control gate to floating gate coupling and leakage current.
Thus, the present invention provides at least the following advantages, in addition to others mentioned in this application:
A process for fabricating a non-volatile memory cell, comprising the steps of: providing a semiconductor body; forming gate insulators over predetermined locations of nonvolatile memory transistors; depositing a first conductive layer comprising more than 50% atomic of silicon in an amorphous (not polycrystalline) condition over said predetermined locations of nonvolatile memory transistors; depositing a dielectric over said first layer; depositing a second conductor layer over said dielectric; and patterning said first and second conductor layers so that, in said predetermined locations of nonvolatile memory transistors, said first conductor layer forms a floating gate and said second conductor layer forms a control gate.
According to the present invention there is also provided: A process for fabricating a capacitor between two conductive layers in integrated circuit manufacture, comprising the steps of: depositing a first conductive layer comprising more than 50% atomic of silicon in an amorphous (and not polycrystalline) condition; depositing a dielectric over said first layer; and depositing a second conductor layer over said dielectric.